Circuit techniques for low-voltage and high-speed A/D by Mikko E. Waltari

By Mikko E. Waltari

This precious monograph offers a complete of 7 prototypes: double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a present steerage DAC with a deglitcher, and pipelined ADCs applying the SO strategies.

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Circuit techniques for low-voltage and high-speed A/D converters

This helpful monograph provides a complete of 7 prototypes: double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a present guidance DAC with a deglitcher, and pipelined ADCs using the SO options.

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Practical versions of such switches have a near-infinite off impedance, and a typical on impedance in the range 90 to 300 Ω. Standard CMOS bilateral switches can be switched at frequen­ cies ranging from zero to several megahertz, and have many uses in low-level power control circuits. They can, for example, be used to replace conventional mechanical switches and relays in signalcarrying applications, the bilateral switch being DC-controlled and placed directly on the printed circuit board (PCB) where it is needed, thus eliminating the problems of signal radiation and interaction that normally occur when such signals are mechanically switched via lengthy cables.

Vi feed a light-depen­ dent voltage to its inverting input. If these two voltages differ by more than a few millivolts the op-amp output is driven to saturation (to near-zero or near-positive-rail values), thus driving Qi and RLA either on or off. If the two voltages are within a few millivolts of each other, the relay state depends on the direction of bridge imbalance. The actual balance point can be preset via RVU and is independent of variations in supply voltage or temperature. Because of the very high gain of the op-amp, the Figure 233 circuit has a far greater sensitivity that the CMOS-aided circuits described earlier.

36. Here, in each power line half-cycle, the R\-C\ network applies a variable phase-delayed version of the half-cycle to the triac gate via the diac, and when the Q voltage rises to 35 V the diacfiresand delivers a 5 V trigger pulse (from Cx) into the triac gate, thus turning the triac on and simultaneously applying power to the lamp load and removing the drive from the R-C network. χ. 37. 37 Quadrac symbol The unijunction transistor The unijunction transistor (UJT) is a 3-terminal trigger device that is often used to trigger SCRs or triacs.

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