By Hubert Kaeslin
This publication supplies a top-down process of designing most recent electronic built-in circuits via protecting all issues of built-in electronic circuit layout inside of over 800 pages.
i will suggest this ebook for those that have already got simple wisdom of IC layout and wish to get a more in-depth glance over the total subject and difficulties that come up in current applied sciences and research.
the writer starts off from the pinnacle point of method integration right down to the CMOS units, physics and their difficulties for designing circuits. He additionally offers info to semiconductor company and workflow of the in addition to performance of EDA tools.
every one Chapters starts off with a number of phrases at the present contexts and ends with a number of brief difficulties for self learning and an appendix with additional info resulting in much more resources.
the data is more advantageous through definitions and plenty of very useful observations. Theories usually comprise actual lifestyles examples and in addition a few instructions for designers, furthermore many examples with information values from current units from well-known brands are given.
not like ordinary books, the writer starts off with architectures and methods, like pipelining, replication and time sharing for enforcing algorithms.
subsequent he explains description languages at the instance of VHDL, but the focal point of this bankruptcy isn't the syntax of VHDL yet processing of VHDL and its effect at the layout. additionally there are a few examples for the most important circuits and instructions which are used inside a design.
this can be by means of timing and clocking ideas for electronic circuits. right here synchronous and asynchronous disciplines and characterizations of all types of part and aspect caused clocks in a layout are defined. This half additionally faces all difficulties of asynchronous information dealing with, and the way to avoid its drawbacks. All reasons are illustrated with worthwhile timing diagrams and figures of universal circuit configurations.
ultimately, it begins to get into gate and transistor point layout. fundamentals of CMOS habit and common sense gates are illustrated, prolonged by means of concerns on strength dissipation, provide voltage drop and noise on a die, actual versions for the layout and electric features. Verification innovations of performance and layout are defined besides the layout move of EDA tools.
a really great and particularly unique a part of the publication is the bankruptcy "VLSI Economics and undertaking Management". there's all type of workflows, price types and industry aspects mentioned and displayed in an overview.
The ebook is finished by means of a bankruptcy on semiconductor physics, performance of CMOS units and outlooks to the CMOS expertise of tomorrow.
As a completely adverse aspect continues to be: there are too many themes. Many difficulties are proven and defined, yet do not have an in depth resolution. the writer countervails this case by way of giving solid references to paintings on additional and aid fabric on the publishers homepage.
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Extra info for Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication
Find acceptable compromises between computational complexity and accuracy. Analyze and contain eﬀects of ﬁnite word-length computation. Decide on number representation schemes. Evaluate alternatives and select the one best suited for the situation at hand. Quantify the minimum required computational resources (in terms of memory, word widths, arithmetic and logic operations, and their frequencies of occurrence). g. signal-to-noise ratio, coding gain, data compression factor, error rate, and the like against speciﬁcations.
Whether the circuit is eventually going to be fabricated as a full-custom IC or as a semi-custom IC is, in principle, immaterial. In either case, physical design does not go beyond place and route (P&R) where each cell is assigned a geometric location and connected to other cells by way of metal lines. As this is done by automatic tools, the resulting layouts are almost always correct by construction and design productivity is much better than for manual layout. Another advantage is that any engineer familiar with electronics design can start to develop cell-based ASICs with little extra training.
Typical application areas are in telecommunications equipment, automotive equipment, instrumentation, and control systems. 10 11 Standard cells are also term ed “b o oks” (within IBM ) and m acros (in the context of sem i-custom ICs). O lder pro cesses did not aﬀord that much routing resources and the wires had to b e inserted b etween the rows such as to form well-deﬁned routing channels. The resulting separation b etween adjacent cell rows obviously m ade a p o or usage of silicon. In fact, it was not uncom m on that routing channels o ccupied twice or even three tim es as much area as the active cells them selves.